1. Field of the Invention
The present invention generally relates to a delay time adjusting circuit and, more particularly, to a delay time adjusting circuit and a delay time adjusting method which circuit and method adjust a delay time of a signal transmitted in a semiconductor integrated circuit.
2. Description of the Related Art
Conventionally, a semiconductor integrated circuit, such as a DDR (Double Data Rate)-SDRAM, which is required to operate at high speed and has a DLL (Delay Locked Loop) circuit mounted thereon, comprises a delay time adjusting circuit to adjust a phase of a clock signal.
FIG. 1 is a circuit diagram of a conventional delay time adjusting circuit. As shown in FIG. 1, the conventional delay time adjusting circuit comprises an input buffer 1, an output buffer 5, frequency dividers 2 and 4, a DLL array 3, a dummy circuit 6, a phase comparator 8 and a delay adjuster 10.
In this conventional delay time adjusting circuit, a clock signal is input into the input buffer 1, which outputs a signal Cin. The frequency divider 2 and the DLL array 3 are connected to the input buffer 1. The frequency divider 4 and the output buffer 5 are connected to an output terminal of the DLL array 3. The frequency divider 2 outputs a target clock signal tclk. The DLL array 3 outputs a signal Cout. The output buffer 5 outputs a clock signal delayed by the DLL array 3. The frequency division rates of the frequency dividers 2 and 4 are equal.
The dummy circuit 6 is connected to the frequency divider 4 and outputs a delay clock signal dclk. The phase comparator 8 is connected to the frequency divider 2 and an output terminal of the dummy circuit 6, and feeds back a result signal ‘out’ to the delay adjuster 10, according to the supplied target clock signal tclk and the fed-back delay clock signal dclk. An output terminal of the delay adjuster 10 is connected to the DLL array 3. The delay adjuster 10 supplies a control signal CS to the DLL array 3.
FIG. 2 is a circuit diagram of the DLL array 3 shown in FIG. 1. As shown in FIG. 2, the DLL array 3 comprises a switching unit 31 including a plurality of parallel-connected switches SW1 to SWn, and inverters INV1 to INVn respectively arranged to correspond to the switches SW1 to SWn. Switching of the switches SW1 to SWn included in the switching unit 31 is controlled by the controlling signal CS supplied by the delay adjuster 10. The signal Cin is delayed by a time td in each of the inverters INV1 to INVn.
In the above-mentioned delay time adjusting circuit, supposing that a delay time at the input buffer 1 is d1 and a delay time at the output buffer 5 is d2, a delay time at the dummy circuit 6 is (d1+d2). Also, supposing that a delay time of the DLL array 3 is d3, the clock signal input into the input buffer 1 and consequently output from the output buffer 5 is delayed by a time (d1+d2+d3).
Also, supposing that delay times at the frequency dividers 2 and 4 are d4, the clock signal input into the input buffer 1 and then input into the phase comparator 8 as the target clock signal talk is delayed by a time (d1+d4). On the other hand, the clock signal input into the input buffer 1 and consequently input into the phase comparator 8 as the delay clock signal dclk is delayed by a time (d1+d3+d4+(d1+d2)).
Accordingly, a difference in the delay times between the target clock signal talk and the delay clock signal dclk is (d1+d2+d3). This difference equals the delay time (d1+d2+d3) of the clock signal input into the input buffer 1 and consequently output from the output buffer 5. Thereby, in order to match phases of the clock signal input into the input buffer 1 and the clock signal output from the output buffer 5, the delay adjuster 10 adjusts the delay time d3 of the DLL array 3 so that the difference (d1+d2+d3) in the delay times between the target clock signal talk and the delay clock signal dclk equals a time corresponding to a number n (1, 2 or other natural numbers) of clocks of the clock signal.
Next, a description will be given, with reference to FIG. 3, of an operation of the above-mentioned conventional delay time adjusting circuit shown in FIG. 1. FIG. 3 is a waveform diagram indicating the operation of the conventional delay time adjusting circuit shown in FIG. 1. First, a signal Cin indicated by FIG. 3-(a) is divided by four by the frequency divider 2, as indicated by FIG. 3-(b), and then is supplied to the phase comparator 8 as the target clock signal tclk. On the other hand, in the DLL array 3, the signal Cin is delayed by a predetermined time, generating a signal Cout indicated by FIG. 3-(c). Then, the signal Cout is divided by four by the frequency divider 4, generating a monitor clock signal mclk indicated by FIG. 3-(d).
Since the frequency dividers 2 and 4 are supposed to have the same structure, a delay time VD of the monitor clock signal mclk with respect to the target clock signal tclk means a delay time in the DLL array 3. It is noted that variable delay stages of the DLL array 3 are assumed to be minimum stages that provide a minimum delay time.
The monitor clock signal mclk is delayed by a fixed time FD regardless of a frequency thereof in the dummy circuit 6, generating a delay clock signal dclk indicated by FIG. 3(e). Then, phases of the delay clock signal dclk and the target clock signal tclk are compared in the phase comparator 8, which judges that the phase of the delay clock signal dclk is a time TD ahead of the phase of the target clock signal tclk. The phase comparator 8 supplies the delay adjuster 10 with a result signal ‘out’ indicating that the phase of the delay clock signal dclk is the time TD ahead of the phase of the target clock signal tclk.
Then, the delay adjuster 10 supplies the DLL array 3 with a control signal CS according to the result signal ‘out’. Then, the delay time in the DLL array 3 is lengthened by the time TD. The above-mentioned operation generates a signal Lon, indicated by FIG. 3-(f), as a delay clock signal dclk so that the phase of the delay clock signal dclk is matched to the phase of the target clock signal tclk.
Next, a description will be given, with reference to FIG. 4, of an operation of the above-mentioned conventional delay time adjusting circuit shown in FIG. 1, in a case where a clock signal having a higher frequency is input into the input buffer 1, as a semiconductor integrated circuit is increasingly required to operate at high speed. FIG. 4 is a waveform diagram indicating the operation of the conventional delay time adjusting circuit shown in FIG. 1. In this case, a signal Cin indicated by FIG. 4-(a), which is supplied to the frequency divider 2 and the DLL array 3, has a higher frequency than the signal Cin indicated by FIG. 3-(a). The signal Cin indicated by FIG. 4-(a) is divided by four by the frequency divider 2, as in the case shown in FIG. 3, and then is supplied to the phase comparator 8 as a target clock signal tclk indicated by FIG. 4-(b). On the other hand, in the DLL array 3, the signal Cin is delayed by a predetermined time, generating a signal Cout indicated by FIG. 4-(c). Then, the signal Cout is divided by four by the frequency divider 4, generating a monitor clock signal mclk indicated by FIG. 4-(d).
Since the frequency dividers 2 and 4 are supposed to have the same structure, a delay time VD of the monitor clock signal mclk to the target clock signal tclk means a delay time in the DLL array 3. It is noted that the variable delay stages of the DLL array 3 are assumed to be minimum stages that provide a minimum delay time.
The monitor clock signal mclk is delayed by the fixed time FD regardless of a frequency thereof in the dummy circuit 6, generating a delay clock signal dclk indicated by FIG. 4-(e). Then, phases of the delay clock signal dclk and the target clock signal tclk are compared in the phase comparator 8.
However, as indicated by FIG. 4-(b) and FIG. 4-(e), when the frequency of the signal Cin is high, the sum of the delay time VD of the minimum stages in the DLL array 3 and the fixed time FD, which is fixed regardless of a frequency, delayed in the dummy circuit 6 may cause the phase of the delay clock signal dclk to be behind the phase of the target clock signal tclk.
There is a problem in this case that since the phase of the delay clock signal dclk is already behind the phase of the target clock signal tclk, the delay time in the DLL array 3 cannot be adjusted so that the phase of the delay clock signal dclk is matched to the phase of the target clock signal tclk by using a first clock of the target clock signal tclk as a target. A case like this is referred to as a so-called underflow state.